Modified Low Power SRAM Compiler with Reduced Access Time
By: Vinay, B. K
.
Contributor(s): Pushpa Mala.
Publisher: New York Springer 2022Edition: Vol,103(6), Dec.Description: 2013–2023p.Subject(s): Electrical EngineeringOnline resources: Click Here
In:
Journal of the institution of engineers (India): Series BSummary: availability of memory designs is a stumbling wedge toward the computer systems research. Memory compilers are commonly absent from current Process Design Kits, and the expensive solutions that are available commercially include memory circuits with immutable cells, with configuration restrictions and stringent licenses. OpenRAM is an open-source memory compiler to develop, characterize and verify memory designs which can be fabricated across multiple technologies and configurations. The proposed OpenRAM architecture employs 12T SRAM memory cell, 45 nm technology, provides for low power consumption, reduced read and write access time and reduced static noise margin over OpenRAM architecture with 6T memory cell. This architecture is energy efficient and radiation hardened to tolerate Single-node Upsets. The proposed SRAM design in OpenRAM has an improvement in execution time by 26.31% and power dissipation by 31.88% as compared to conventional 12T SRAM (Qi in IEEE Trans Device Mater Reliab 16(3): 388–395, 2016). Further, a considerable improvement in static noise margin of ~ 23% as compared to other conventional SRAM cells (as reported by Jung in: Proc IEEE 55th Int MWSCAS, 2012, Guo in IEEE Trans Very Large Scale Integr Syst 26(5) 991–994, 2018, Qi in IEEE Trans Device Mater Reliab 16(3): 388–395, 2016) is achieved.
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availability of memory designs is a stumbling wedge toward the computer systems research. Memory compilers are commonly absent from current Process Design Kits, and the expensive solutions that are available commercially include memory circuits with immutable cells, with configuration restrictions and stringent licenses. OpenRAM is an open-source memory compiler to develop, characterize and verify memory designs which can be fabricated across multiple technologies and configurations. The proposed OpenRAM architecture employs 12T SRAM memory cell, 45 nm technology, provides for low power consumption, reduced read and write access time and reduced static noise margin over OpenRAM architecture with 6T memory cell. This architecture is energy efficient and radiation hardened to tolerate Single-node Upsets. The proposed SRAM design in OpenRAM has an improvement in execution time by 26.31% and power dissipation by 31.88% as compared to conventional 12T SRAM (Qi in IEEE Trans Device Mater Reliab 16(3): 388–395, 2016). Further, a considerable improvement in static noise margin of ~ 23% as compared to other conventional SRAM cells (as reported by Jung in: Proc IEEE 55th Int MWSCAS, 2012, Guo in IEEE Trans Very Large Scale Integr Syst 26(5) 991–994, 2018, Qi in IEEE Trans Device Mater Reliab 16(3): 388–395, 2016) is achieved.
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